D a t a S h ee t , R e v . 2, J a n . 20 0 5
TE3-LIU™
Line Interface Unit for DS3, STS 1 and E3
PEF 3452, Version 1.3
Wireline Communications
N e v e r
s t o p
t h i n k i n g .
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®,
FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®,
MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®, QUAT®, QuadFALC®,
SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG.
10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG.
Microsoft® is a registered trademark of Microsoft Corporation, Linux® of Linus Torvalds,
Visio® of Visio Corporation, and FrameMaker® of Adobe Systems Incorporated.
The information in this document is subject to change without notice.
Edition 2005-01-24
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 1/24/05.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TE3-LIU™
Revision History:
2005-01-24
Rev. 2
Previous Version:
Preliminary Data Sheet TE3-LIU V1.3, 2001-12-05, DS1
Page
Subjects (major changes since last revision)
Page 49
Table 17
wg_template_fm5_a5_2003-09-01.fm / DS4
PEF 3452
TE3-LIU V1.3
Table of Contents
Page
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
3.1
3.2
3.3
3.3.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
26
27
27
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.5.1
4.1.5.2
4.1.5.3
4.1.6
4.1.6.1
4.1.6.2
4.1.6.3
4.1.7
4.1.8
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.6.1
4.2.6.2
4.2.6.3
4.2.7
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Receiver Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Monitoring Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Line Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMI Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B3ZS Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDB3 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alarm Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3 LOS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STS-1 LOS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E3 LOS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intrinsic Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Line Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMI Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B3ZS Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDB3 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AIS Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
30
30
31
32
33
33
33
33
34
34
34
34
35
36
37
38
38
39
40
41
42
42
42
42
42
43
Data Sheet
4
10
11
13
14
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Table of Contents
Page
4.3
4.4
4.4.1
4.4.2
Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remote Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
44
44
45
5
5.1
5.2
5.3
5.4
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Line Inactive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
46
46
46
46
6
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.7.1
6.4.7.2
6.4.7.3
6.5
6.6
6.7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Attenuator Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Template E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Template DS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Template STS-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
47
48
49
51
51
52
53
55
56
57
58
58
59
61
63
63
64
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8
8.1
8.2
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cable Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
5
66
66
67
68
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Data Sheet
Page
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T3/T1 Multiplexer Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channelized T3 Link Layer Application . . . . . . . . . . . . . . . . . . . . . . . .
Unchannelized T3 Link Layer Application . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3 Line Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E3 Loss of Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Tolerance Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Attenuation Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remote Loop Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Loop Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Pulling Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XCLK Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RCLK Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E3 Pulse Shape at Transmitter Output . . . . . . . . . . . . . . . . . . . . . . . .
DS3 Pulse Shape at the Cross Connect Point (450 ft.) . . . . . . . . . . . .
STS-1 Pulse Shape at the Cross Connect Point (450 ft.) . . . . . . . . . .
Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Waveforms for AC Testing . . . . . . . . . . . . . . . . . . . . . . .
DS3 Cable Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
13
14
14
14
16
26
30
31
32
35
36
37
38
39
41
44
45
51
52
53
53
54
55
56
57
58
59
61
63
64
66
67
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Data Sheet
Page
Interface Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Indication Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Component Values for Receiver . . . . . . . . . . . . . . . . . . . . . .
External Component Values for DS Line Monitoring . . . . . . . . . . . . . .
E3 Receive Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Jitter Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Component Values for Transmitter . . . . . . . . . . . . . . . . . . . .
E3 Transmit Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Attenuation PLL Operation Frequencies . . . . . . . . . . . . . . . . . . .
Transmit Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REFCLK Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL Crystal Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Select Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . .
XCLK Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RCLK Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E3 Pulse Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3 Pulse Mask (ANSI T1.404, GR-499-CORE) . . . . . . . . . . . . . . . .
DS3 Pulse Mask (ANSI T1.404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3 Pulse Mask (GR-499-CORE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STS-1 Pulse Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STS-1 Pulse Mask (ANSI T1.102) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Characteristic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
17
20
23
24
27
29
30
31
32
36
38
39
40
41
47
48
49
51
52
53
54
55
56
57
58
59
60
60
61
61
63
63
64
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Preface
The PEF 3452 (TE3-LIU™) is a flexible line interface unit for a wide area of
telecommunication and data communication applications. The device is addressed to
fulfill all requirements to build a DS3, STS-1 or E3 line interface.
Organization of this Document
This Data Sheet is organized as follows:
•
Overview
Gives a general description of the product, lists the key features, and presents some
typical applications.
•
Pin Descriptions
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.
•
Functional Description
Describes the functional blocks and principle operation modes.
•
Interface Description
Describes the device interfaces.
•
Operational Description
Shows the operation modes and how their initialization.
•
Electrical Characteristics
Specifies maximum ratings, DC and AC characteristics.
•
Package Outlines
Shows the mechanical values of the device package.
•
Appendix
•
Index
Data Sheet
2005-01-24
PEF 3452
TE3-LIU V1.3
Related Documentation
This document refers to the following international standards
(in alphabetical/numerical order):
ACA TS016 (general requirements for Australia)
CTR-24/TBR-24 (E3 requirements)
ETS 300 166 (E3 transmit return loss)
ITU-T G.703 (E3 pulse mask, B3ZS/HDB3 code, E3 receive return loss)
ITU-T G.751 (jitter requirements E3)
ITU-T G.775 (loss of signal definition)
ITU-T G.823 (jitter requirements E3)
ITU-T G.824 (jitter requirements DS3)
ITU-T O.151 (pseudo random binary sequence (PRBS) definition)
GR-253-CORE (STS-1 jitter requirements)
GR-499-CORE (DS3 pulse mask, DS3 jitter requirements)
ANSI T1.102 (STS-1 pulse mask)
ANSI T1.102 Annex B (DS3 monitoring)
ANSI T1.231 (maintenance functions, defect definitions)
ANSI T1.404 (DS3 pulse mask)
MIL-STD 883D (ESD requirements)
Your Comments
We welcome your comments on this document. We are continuously trying improving
our documentation. Please send your remarks and suggestions by e-mail to
com.docu_comments@infineon.com
Please provide in the subject of your e-mail:
device name (TE3-LIU™), device number (PEF 3452), device version (Version 1.3),
and in the body of your e-mail:
document type (Data Sheet), issue date (2005-01-24) and document revision number
(Rev. 2).
Data Sheet
2005-01-24
PEF 3452
TE3-LIU V1.3
Overview
1
Overview
The TE3-LIU™ PEF 3452 Line Interface Unit is used to connect a DS3/STS-1 or E3
framer device to an analog transmission line. The line interface fulfills the relevant
standards for DS3 (44.736 Mbit/s), STS-1 (51.840 Mbit/s) and E3 (34.368 Mbit/s)
systems.
The TE3-LIU™ comes in a P-MQFP-44-2 package (SMD) to save a significant amount
of board space. The integrated jitter attenuation further reduces overall system
complexity and cost.
This CMOS 3.3 V low power device contains an integrated pulse shaper to drive any line
length within the range of up to 1100 ft. without the need for external length selection
(Line Build Out).
The hardware configuration mode allows low cost systems with flexible device setting
without the need for a microprocessor.
An optional microprocessor mode allows the connection to a standard microprocessor
bus to control hardware settings.
Data Sheet
10
Rev. 2, 2005-01-24
Line Interface Unit for DS3, STS1 and E3
TE3-LIU™
PEF 3452
Version 1.3
1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
Generic analog interface for all DS3/STS-1/E3
applications
Single chip solution for receive and transmit direction
3.3 V low power device
Integrated receive equalization network
Integrated noise and crosstalk filter
Clock and data recovery using an integrated PLL
P-MQFP-44-2
with ultra-low intrinsic jitter
Transmit clock duty cycle correction PLL
No external components required for clock and data
recovery and receive equalizer
DSX receive line monitor (additional 20 dB gain according to ANSI T1.102)
Low transmitter output impedances for high transmit return loss
Disable function of the analog transmit line outputs
Transmit pulse shaper to fulfill requirements of ANSI T1.404,
Telcordia GR-499-CORE, ANSI T1.102 and ITU-T G.703 (E3)
Maximum line length up to 1100 ft. (using standard coaxial cable, for example AT&T
728A, 734A or 734D)
External line length selection (LBO) is not required
Jitter specifications of GR-499-CORE and ITU-T G.823 are met
Integrated jitter attenuation PLL and buffer in transmit direction
Dual or single rail digital inputs and outputs from/to the framer interface
Selectable line codes (HDB3 (E3), B3ZS (DS3/STS-1), AMI)
Analog and digital loss of signal detection and indication
Automatic RDOP/RDON blanking option in case of LOS
Bipolar violation indication
Local loop and remote loop for diagnostic purposes
Insertion of alarm indication signal ("all ones")
Flexible hardware or software controlled device configuration
Device power down function
Type
Package
PEF 3452
P-MQFP-44-2
Data Sheet
11
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Overview
Hardware Interface Mode
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DS3/STS-1 or E3
Line Coding (E3: HDB3 or AMI; DS3/STS-1: B3ZS or AMI)
Transmitter disable
Power down
Remote loop
Local loop
Single/dual rail operation
Receive clock edge selection
Transmit clock edge selection
Transmit "all ones"
Receive line monitoring mode
Automatic RDOP/RDON blanking option
Jitter attenuation
Loss of signal indication
Bipolar violation indication
Microprocessor Interface Mode
•
•
Microprocessor bus compatible interface
Hardware control lines directly accessible
General
•
•
•
•
•
•
CMOS device
P-MQFP-44-2 package (body size 10 mm × 10 mm, lead pitch 0.8 mm)
Single power supply: 3.3 V ± 5%
5V-tolerant digital input lines
Temperature range of -40°C to +85°C
Low power device
Applications
•
•
•
•
•
•
Interface for SONET/DS3 and E3 network equipment
WAN gateways
CSU/DSU
Multiplexers
Digital crossconnect systems
DS3/STS-1/E3 Test Equipment
Data Sheet
12
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Overview
TMS
TCK
TDI
TRS
TDO
REFCLK
VDD
VSS
VDDRP
VSSRP
Logic Symbol
VDDR
VSSR
1.2
RDOP
RDON/BPV
RCLK
RL1
RL2
PEF 3452
TE3-LIUTM
XTAL1
XTAL2
XL1
LOS
XDIP
XDIN
XCLK
XL2
Figure 1
Data Sheet
DR/SR
XPE
RPE
MON
RL
LL
LCODE
XAIS
XLT
BLE
CS
DS3/STS-1
DS3/E3
JATT
RES
VDDXP
VSSXP
VDDX
VSSX
HW + µP Access
F0229
Logic Symbol
13
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Overview
1.3
Typical Applications
Figure 2 to Figure 4 show typical applications using the TE3-LIU™.
28 x
DS1
digital
QuadLIUTM
#1
DS1 #1
analog
QuadLIUTM
#7
DS1 #28
analog
DS3
digital
DS3
analog
TE3_LIUTM
TE3-MUXTM
F0087
Figure 2
T3/T1 Multiplexer Application
DS3
analog
TE3CHATTTM
TE3-LIUTM
F0217
Figure 3
Channelized T3 Link Layer Application
DS3
analog
TE3-LIUTM
TE3-MUXTM
DSCC4
F0140
Figure 4
Data Sheet
Unchannelized T3 Link Layer Application
14
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Overview
Note: TE3-MUX™ (PEB 3445) is an M13 MUltipleXer/demultiplexer with an integrated
DS3 framer
QuadLIU™ (PEB 22504) is a 4-channel Line Interface Unit for E1/T1/J1
DSCC4™ (PEB 20534) is a 4-channel Serial Communication Controller
TE3-CHATT™ (PEB 3456) is a CHAnnelized T3 Termination with DS3
Framer, M13 Multiplexer, T1/E1 Framers and 256 Channel HDLC/PPP
controller
Data Sheet
15
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Pin Descriptions
2
Pin Descriptions
2.1
Pin Diagram
TRS
33
34
31
29
27
25
CS
RDON/BPV
RDOP
RCLK
VDD
VSS
REFCLK
XCLK
XDIP
XDIN
RES
P-MQFP-44-2 (top view)
23
22
TDI
TMS
XLT
20
36
VDDXP
XTAL2
38
18
PEF 3452
TE3-LIUTM
40
16
XAIS
BLE
14
42
JATT
MON
LCODE
RL2
RL1
DR/SR
VDDR
12
11
9
VSSR
XPE
7
RPE
5
DS3/STS1
XL2
VSSX
3
DS3/E3
44
1
XL1
VDDX
VDDRP
VSSRP
TCK
TDO
RL
LL
XTAL1
VSSXP
LOS
F0230
Figure 5
Data Sheet
Pin Configuration
16
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Pin Descriptions
2.2
Table 1
Pin No.
Pin Definitions and Functions
Interface Pin Functions
Symbol
Input (I)
Output (O)
Supply (S)
Function
Receive Direction
9
RL1
I (analog)
Line Receiver 1
Analog input from the external transformer
(receive bipolar ring).
The signal at RL1 must be coded according
to B3ZS or HDB3.
10
RL2
I (analog)
Line Receiver 2
Analog input from the external transformer
(receive bipolar tip).
The signal at RL1 must be coded according
to B3ZS or HDB3.
25
RDOP
O
Receive Data Output/Positive
Received data at RL1/2 is sent on
RDOP/RDON to the framer interface. Data
is clocked with the rising or falling edge of
RCLK, depending on RPE.
In single rail mode (DR/SR=0), data is sent
in NRZ format.
24
RDON
O
Receive Data Output/Negative
If dual rail data format is selected, the
negative data signal is output on
RDON/BPV.
BPV
26
Data Sheet
RCLK
Bipolar Violation
If single rail data format is selected, the
bipolar violation indication signal is output
on RDON/BPV. BPV is synchronized on
RCLK.
O
Receive Clock
Receive Clock extracted from the incoming
data pulses. The active clock edge is
determined by RPE.
During LOS, a clock signal is generated
internally and driven on RCLK (derived
from REFCLK).
17
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Pin Descriptions
Table 1
Pin No.
Interface Pin Functions (cont’d)
Symbol
Input (I)
Output (O)
Supply (S)
Function
Transmit Direction
1
XL1
O (analog)
Transmit Line 1 (transmit bipolar ring)
Analog output to the external transformer.
XL1 can be switched into inactive mode.
3
XL2
O (analog)
Transmit Line 2 (transmit bipolar tip)
Analog output to the external transformer.
XL2 can be switched into inactive mode.
31
XDIP
I + PU
Transmit Data In/Positive
Transmit data received from the framer
interface to be output on XL1/2. NRZ or
dual rail positive data has to be provided at
XDIP. Latching of data is done with the
rising or falling transitions of XCLK,
depending on XPE.
32
XDIN
I + PU
Transmit Data In/Negative
If dual rail format is selected, negative data
signal is read from XDIN. If single rail data
format is selected, data on XDIN is ignored.
Latching of data is done with the rising or
falling transitions of XCLK, depending on
XPE.
30
XCLK
I + PU
Transmit Clock
Input of the working clock for the
transmitter. The active clock edge is
determined by XPE.
DS3: 44.736 MHz
STS-1: 51.840 MHz
E3: 34.368 MHz
To fulfill e.g. ITU-T G.832 a clock accuracy
of 20 ppm is required. For correct function
a clock signal has always to be supplied to
XCLK.
Data Sheet
18
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Pin Descriptions
Table 1
Pin No.
Interface Pin Functions (cont’d)
Symbol
Input (I)
Output (O)
Supply (S)
Function
I
Reference Clock
REFCLK is the basic internal clock. It must
be stable during reset and operation.
This clock is also used to synchronize the
receive PLL in case of no signal.
Global Clock Reference
29
REFCLK
The clock frequency depends on the target
application:
DS3: 44.736 MHz
STS-1: 51.840 MHz
E3: 34.368 MHz
To fulfill e.g., ITU-T G.832 a clock accuracy
of 20 ppm is required.
39
XTAL1
I
38
XTAL2
O
Jitter Attenuation Reference
Connection for an external pullable crystal.
DS3:
14.912 MHz
STS-1: 17.280 MHz
E3:
11.456 MHz
If jitter attenuation is disabled (default),
XTAL1 is internally driven to a fixed level
(not floating).
Data Sheet
19
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Pin Descriptions
Table 2
Control Pin Functions
Pin No.
Symbol
Input (I)
Output (O)
Supply (S)
Function
33
RES
I
Hardware Reset
A low signal at this pin forces the device
into reset state.
23
CS
I + PU
Chip Select
0 = hardware control signals are switched
through
1 = hardware control signals are ignored
5
DS3/E3
I + PU
DS3/STS-1 or E3 Select
Primary mode selection. This signal has to
be stable during reset and may not change
afterwards. It must not be connected to a
µP bus.
0 = E3
1 = DS3 or STS-1 (see DS3/STS-1)
4
DS3/STS-1
I + PU
DS3 or STS-1 Select
Primary mode selection. This signal has to
be stable during reset and may not change
afterwards. It must not be connected to a
µP bus.
0 = STS-1
1 = DS3
13
LCODE
I + PU
Line Code Select
for receive and transmit direction
E3:
0 = AMI
1 = HDB3
DS3/STS-1:
0 = AMI
1 = B3ZS
16
Data Sheet
XAIS
I + PU
Transmit Alarm Indication
0 = no AIS
1 = AIS all-ones insertion
20
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Pin Descriptions
Table 2
Control Pin Functions (cont’d)
Pin No.
Symbol
Input (I)
Output (O)
Supply (S)
Function
20
RL
I + PU
Remote Loop Switching
0 = no loop
1 = Remote Loop1)
19
LL
I + PU
Local Loop Switching
0 = no loop
1 = Local Loop1)
21
XLT
I + PU
Transmitter inactive
0 = transmitter enabled
1 = transmitter disabled
(outputs 1.5 V common mode voltage)
14
MON
I + PU
Line Monitoring Mode
0 = additional 20 dB gain at RL1/RL2
1 = normal
15
BLE
I + PU
Blanking Enable
0 = detected signal is switched through
even in case of LOS
1 = all-zero signal is sent on RDOP/RDON
in case of LOS, REFCLK is used to drive
RCLK
12
DR/SR
I + PU
Dual Rail/Single Rail Select
The framer interface is operated either in
dual rail or single rail mode. In single rail
mode, the BPV signal is output on
RDON/BPV and input on XDIN is ignored.
0 = single rail
1 = dual rail
6
RPE
I + PU
RCLK Positive Edge Selection
0 = RDOP, RDON are clocked with
negative (falling) edge of RCLK
1 = RDOP, RDON are clocked with positive
(rising) edge of RCLK
7
XPE
I + PU
XCLK Positive Edge Selection
0 = XDIP, XDIN are clocked with negative
(falling) edge of XCLK
1 = XDIP, XDIN are clocked with positive
(rising) edge of XCLK
Data Sheet
21
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Pin Descriptions
Table 2
Control Pin Functions (cont’d)
Pin No.
Symbol
Input (I)
Output (O)
Supply (S)
Function
43
JATT
I + PD
Jitter Attenuation Enable
This signal has to be stable during reset
and may not change afterwards. It must not
be connected to a µP bus.
0 = no jitter attenuation (default if left open)
1 = jitter attenuation in transmit direction
22
LOS
O
Loss of Signal Indication
0 = correct signal
1 = loss of signal
LOS is synchronized on RCLK. During
LOS, a clock signal is generated internally
and driven on RCLK.
1) If RL=LL=1, the device is set into power down mode.
Data Sheet
22
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Pin Descriptions
Table 3
Power Supply Pins
Pin No.
Symbol
Input (I)
Output (O)
Supply (S)
Function
11
VDDR
S (analog)
Positive Power Supply
for the analog receiver
8
VSSR
S (analog)
Power Supply Ground
for the analog receiver
44
VDDX
S (analog)
Positive Power Supply
for the analog transmitter
2
VSSX
S (analog)
Power Supply Ground
for the analog transmitter
18
VDDRP
S (analog)
Positive Power Supply
for the analog receiver PLL
17
VSSRP
S (analog)
Power Supply Ground
for the analog receiver PLL
37
VDDXP
S (analog)
Positive Power Supply
for the analog transmitter PLL
40
VSSXP
S (analog)
Power Supply Ground
for the analog transmitter PLL
27
VDD
S
Positive Power Supply
for digital subcircuits and the digital
receiver output
28
VSS
S
Power Supply Ground
for digital subcircuits and the digital
receiver output
Data Sheet
23
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Pin Descriptions
Table 4
Test Pins1)
Pin No.
Symbol
Input (I)
Output (O)
Supply (S)
Function
34
TRS
I + PU
TAP Controller Reset
Active low test controller reset; this pin
must be connected to RST or VSS
35
TDI
I + PU
Test Data Input
36
TMS
I + PU
Test Mode Select
41
TCK
I + PU
Test Clock
42
TDO
O
Test Data Output
1) These pins are used for factory test only; boundary scan mode is not provided.
Note: PU = input or input/output comprising an internal pullup device
PD = input or input/output comprising an internal pulldown device
To override the internal pullup (pulldown) by an external pulldown (pullup),
a resistor value of 47 kΩ is recommended.
Unused pins containing pullups or pulldowns can be left open.
Data Sheet
24
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Functional Description
3
Functional Description
3.1
Functional Overview
The TE3-LIU™ device contains analog and digital functional blocks, which are
configured and controlled by direct hardware or microprocessor control.
The main interfaces are
•
•
•
•
Receive Line Interface
Transmit Line Interface
Framer Interface
Hardware Interface
The main internal functional blocks are
•
•
•
•
•
•
Analog line receiver with noise & crosstalk filter, equalizer network and clock/data
recovery
Analog line driver with programmable pulse shaper
Central clock generation module
Jitter attenuator
Maintenance functions (e.g., loop switching local or remote)
Hardware/microprocessor control interface
Data Sheet
25
Rev. 2, 2005-01-24
Figure 6
Data Sheet
26
XL2
XL1
Local
Loop
XLT
Line
Driver
& LBO
LL
Noise
Filter
Hardware/µP Interface
MON
20 dB
Gain
Stage
Mode
Control
Pulse
Shaper
Transmit
PLL
Var. Gain
Amplifier
Test Mode Control
XAIS
AIS
Insertion
XTAL1
XTAL2
JATT
REFCLK
Clock &
Data
Recovery
LOS, BLE
ALOS
Detection
TRS
General
Control
Jitter
Attenuator
Buffer
Jitter
Attenuator
PLL
Equalizer
Level
Detection
Remote
Loop
DR/SR
LCODE
DS3/STS1/E3
Encoder
F0231
XCLK
XDIP
XDIN
RL
RCLK
RDOP
RDON/BPV
Decoder
DR/SR
LCODE
DS3/STS1/E3
LOS
LOS
Detection
3.2
RL2
RL1
Autom.
Gain
Control
PEF 3452
TE3-LIU V1.3
Functional Description
Block Diagram
RES
TCK
TMS
TDI
TDO
REFCLK
DS3/E3
DS3/STS-1
JATT
XAIS
LCODE
XPE
RPE
XLT
MON
LL
RL
DR/SR
BLE
CS
LOS
Block Diagram
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Functional Description
3.3
Functional Blocks
3.3.1
Hardware Control Unit
All hardware control signals except DS3/E3, DS3/STS-1 and JATT are gated by CS. All
other control signals are gated by CS to allow an easy connection to a microprocessor
(µP) data bus. DS3/E3, DS3/STS-1 and JATT may not be connected to a data bus. If
direct hardware control without µP is intended, CS has to be connected to VSS.
After reset all control input values are cleared. The default control values (driven by
internal pullups) are activated after CS = low is applied for the first time after reset.
Table 5
Hardware Control Functions
Device Function
Control Signal
Selection of E3 or DS3/STS-1 mode1)
DS3/E3
0 = E3
1 = DS3 or STS-12)
Selection of DS3 or STS-1 mode1)
DS3/STS-1
0 = STS-1
1 = DS32)
This pin is ignored, if E3 mode is selected
by DS3/E3 = 0
Dual rail select
DR/SR
0 = single rail data on RDOP and XDIP
1 = dual rail data on RDOP/RDON and
XDIP/XDIN2)
Receive clock edge selection
RPE
0 = data change on negative edge
1 = data change on positive edge2)
Transmit clock edge selection
XPE
0 = data change on negative edge
1 = data change on positive edge2)
Selection of line coding
LCODE
0 = AMI
1 = HDB3 (E3)2)
1 = B3ZS (DS3/STS-1)2)
Send AIS (all-ones alarm indication signal) XAIS
0 = no insertion
1 = AIS insertion2)
Data Sheet
27
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Functional Description
Table 5
Hardware Control Functions (cont’d)
Device Function
Control Signal
Select remote loop
RL
0 = normal operation
1 = remote loop
Select local loop
LL
0 = normal operation
1 = local loop
Select power down mode
LL & RL
00 = normal operation
01 = remote loop operation
10 = local loop operation
11 = power down2)
Blanking enable
BLE
0 = data signal is switched through even in
case of LOS
1 = all-zero signal is transmitted on
RDOP/RDON in case of LOS using RCLK
derived from REFCLK2)
Line monitoring mode
MON
0 = additional 20 dB gain stage activated
1 = normal amplifier setting2)
Transmitter inactive mode
XLT
0 = normal operation
1 = inactive2)3)4)
Jitter attenuation enable
JATT
0 = jitter attenuation disabled2)
1 = jitter attenuation enabled
1) to be selected while reset is active (RST = 0)
2) default, if pin is left open and CS has been asserted at least once
3) outputs 1.5 V common mode voltage
4) connecting of CS to VSS or asserting CS in parallel to RES suppresses spurious output on XL1/2
Data Sheet
28
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Functional Description
Table 6
Hardware Indication Signals
Device Function
Indication Signal
Indicate LOS (loss of signal)
LOS
0 = normal signal
1 = loss of signal
Indicate BPV (bipolar violation)
BPV
0 = no violation
1 = bipolar violation
Available in single rail mode only on pin
RDON/BPV.
Data Sheet
29
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4
Interface Description
4.1
Receiver
4.1.1
Standard Receiver Application
1:1
75 Ω
RL1
C1
R1
TE3-LIUTM
RL2
F0080
Figure 7
Receiver Configuration
Table 7
External Component Values for Receiver
Parameter
Characteristic Line Impedance [Ω]
DS3
STS-1
E3
75
R1 (± 1 %) [Ω]
C1 (± 20 %) [nF]
t2 : t1
75
100
1:1
The external components are the same for DS3, STS-1 and E3 applications.
Data Sheet
30
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.1.2
Line Monitoring Application
DSX cross connect point
75 Ω
1:1
75 Ω
RL1
C1
R1
TE3-LIUTM
Receiver Mode
RL2
MON=1
R3
1:1
RL1
C1
R2
TE3-LIUTM
Monitor Mode
RL2
MON=0
F0081
Figure 8
DS3 Line Monitoring
Table 8
External Component Values for DS Line Monitoring
Parameter
Values
R1 (± 1 %) [Ω]
R2 (± 1 %) [Ω]
R3 (± 1 %) [Ω]
C1 (± 20 %) [nF]
t2 : t1
75
47
470
100
1:1
The external components are according to ANSI T1.102 Annex B. The dimensions given
above lead to a signal level at the monitor device input of approximately -20 dB below
the level at the receiver device.
Similar configurations using the line monitoring mode are possible in STS-1 or E3
applications.
Data Sheet
31
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.1.3
Receive Line Interface
The receive line interface consists of a pre-amplifier, a noise and crosstalk filter, a
variable gain amplifier and an equalizer followed by the clock and data recovery.
The noise and crosstalk filter reduces distortions within the incoming analog signal. The
VGA amplifies the analog signal and the equalizer compensates the frequency
dependent line attenuation. Digital signal levels are formed within the retiming block of
the clock and data recovery.
Receive return loss requirements of ITU-T G.703 are fulfilled as required for E3
operation.
Table 9
E3 Receive Return Loss
Frequency Range
Return Loss
from [kHz]
to [kHz]
[dB]
860
1720
12
1720
34368
18
34368
51550
14
The equalizer contains an additional 20 dB gain stage, which is used in line monitoring
mode to amplify resistively attenuated signals.
Reference Clock
RL1
RL2
20 dB
Gain
Stage
Noise &
Crosstalk
Filter
Automatic
Gain
Control
Level
Detection
False
Lock
Detection
Variable
Gain
Amplifier
Equalizer
Receive
PLL
Receive Clock
Retiming
Dual Rail Receive Data
MON
F0094 V1.3
Figure 9
Data Sheet
Receive Clock System
32
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.1.4
Receive Clock and Data Recovery
The receive clock and data recovery extracts the route clock RCLK from the digital data
stream and converts the data stream into a dual rail bit stream. The clock and data
recovery needs a reference clock to keep the PLL stable during times without data signal
at RL1/RL2. The clock that is output on pin RCLK is the recovered clock of the signal
provided on RL1/RL2 and has a duty cycle close to 50 %. The intrinsic jitter generated
in the absence of any input jitter is defined in Chapter 4.1.8. The PLL reference clock is
generated internally without the need for external components.
4.1.5
Receive Line Coding
In E3 applications the HDB3 and the AMI coding is provided for the data received from
the ternary interface. In DS3/STS-1 mode the B3ZS and AMI code is supported. In B3ZS
or AMI code all code violations are detected and indicated.
4.1.5.1
AMI Code
The AMI code is defined as a dual rail data signal, where the combinations 00 ("0"), 10
("+1") and 01 ("-1") are valid. No subsequent "+1" or "-1" bits are allowed, these will be
detected as bipolar violations and indicated on pin RDON/BPV, if single rail mode is
selected (according to ANSI T1.231 chapter 7.1).
The received AMI data stream is either switched transparently to the framer interface as
dual rail data or converted into a single rail data stream.
4.1.5.2
B3ZS Code
In the B3ZS line code each block of three consecutive zeros is replaced by either of two
replacements codes which are B0V and 00V, where B represents a pulse which applies
to the bipolar rule ("+1" or "-1") and V represents a bipolar violation (two consecutive "+1"
or "-1" bits). The replacement code is chosen in a way that there is an odd number of
valid B pulses between consecutive V pulses to avoid the introduction of a DC
component into the analog signal.
The receive line decoder decodes the incoming B3ZS data signal and changes the
replacement patterns to the original three-zeros pattern. Pattern sequences violation
these rules are reported as bipolar violation errors.
Data output to the framer interface can be selected to be either dual rail or single rail.
Data Sheet
33
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.1.5.3
HDB3 Code
In the HDB3 line code each block of four consecutive zeros is replaced by either of two
replacements codes which are B00V and 000V, where B represents a pulse which
applies to the bipolar rule ("+1" or "-1") and V represents a bipolar violation (two
consecutive "+1" or "-1" bits). The replacement code is chosen in a way that there is an
odd number of valid B pulses between consecutive V pulses to avoid the introduction of
a DC component into the analog signal.
The receive line decoder decodes the incoming HDB3 data signal and changes the
replacement patterns to the original three-zeros pattern. Pattern sequences violation
these rules are reported as bipolar violation errors.
Data output to the framer interface can be selected to be either dual rail or single rail.
4.1.6
Alarm Handling
The receive line interface includes the alarm detection for loss of signal (LOS). LOS is
indicated either if an analog or a digital loss of signal condition is detected.
During LOS a clock signal is sent on RCLK. The clock is internally derived from REFCLK.
4.1.6.1
DS3 LOS Definition
Detection and recovery of digital LOS defects in DS3 mode is done according to ANSI
T1.231:
An LOS defect occurs when 175 contiguous pulse positions with no pulses of either
positive or negative polarity at the line interface are detected. An LOS defect is
terminated upon detecting an average pulse density of at least 33% over a period of 175
contiguous pulse positions following the receipt of a pulse. An LOS defect shall not be
terminated if, at the end of the pulse-position interval, any subintervals of 100 pulse
positions contain no pulses of either polarity.
4.1.6.2
STS-1 LOS Definition
Detection and recovery of digital LOS defects in STS-1 mode is defined in ANSI T1.231
(chapter 8.1.2.1.1) as follows:
An LOS defect occurs upon detection of no transitions on the incoming signal (before
descrambling) for time T, where 2.3 ≤ T ≤ 100 µs.
The LOS defect is terminated after a time period equal to the greater of 125 µs or 2.5×T’
containing no transition-free interval of length T’, where 2.3 ≤ T’ ≤ 100 µs.
Data Sheet
34
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.1.6.3
E3 LOS Definition
Analog LOS is detected, if the signal level on pins RL1/2 drops below a fixed level ("B")
for a certain period. Loss of signal level "B" is defined to be between 15 and 35 dB below
normal signal level "A". If the signal exceeds 35 dB for 175 contiguous pulse periods,
analog LOS defect is indicated.
Analog LOS defect is cleared, if the signal exceeds a threshold of 15 dB below nominal
level for 175 contiguous pulse periods (10 ≤ N ≤ 255). See ITU-T G.775 for reference.
A
B
see ITU-T G.775 page 4
0 dB
3 dB
Level below Nominal
Maximum cable loss
Nominal value
"transition condition" must
be detected
15 dB
Tolerance range, "no transition condition" or "transition
condition" may be declared
"no transition condition"
must be detected
35 dB
F0101 V1.2
Figure 10
E3 Loss of Signal Definition
Data Sheet
35
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.1.7
Jitter Tolerance
Input Jitter Amplitude
The TE3-LIU™ receiver’s tolerance to input jitter complies to and exceeds the relevant
international standards. Especially the requirements of Telcordia GR-499-CORE (DS3),
ITU-T G.824 (DS3), GR-253-CORE (STS-1) and ITU-T G.823 (E3) are fulfilled and
exceeded. Figure 11 and Table 10 show the different input jitter specifications. Low
frequency jitter is called "wander", where the defined border between jitter and wander
is 10 Hz for DS3/E3 and 100 Hz for STS-1.
A1
pass
A2
fail
A3
F1
F2
F3
Jitter Frequency
Figure 11
Jitter Tolerance Principle
Table 10
Input Jitter Requirements
Reference
A1
A2
A3
F1
F4
F5
F6
F0085
F2
F3
[UIPP]
F4
F5
F6
[Hz]
GR-499-CORE,
Category I
5
0.1
not
def.
10
2300
60 ×
103
300 × not
def.
103
not
def.
GR-499-CORE,
Category II
10
0.3
not
def.
10
669
22.3
× 103
300 × not
def.
103
not
def.
GR-253-CORE,
Category II
15
1.5
0.15
10
30
300
2×
103
not
def.
ITU-T G.823
& ETSI TBR24
1.5
0.15
not
def.
100
1000
10 ×
103
800 × not
def.
103
ITU-T G.824
18 µs 5
0.1
not
def.
1.2 ×
10-5
10
600
Data Sheet
36
20 ×
103
30 ×
103
not
def.
400 ×
103
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
100
10
Jitter Amplitude [UI]
pass area
1
fail area
0,1
0,01
0,10
1,00
10,00
100,00
1000,00
10000,00
100000,00
1000000,00
Jitter Frequency [Hz]
GR-499-CORE Cat. 1
GR-499-CORE Cat. 2
ITU-T G.823
ITU-T G.824
GR-253-CORE Cat. 2
TE3-LIU
PUCCINI
TE3-LIU
F0104
F0104
Figure 12
Jitter Tolerance
GR-499-CORE Jitter Tolerance Requirements (DS3)
The input jitter tolerance is defined as the minimum amplitude of sinusodial jitter at a
given frequency that when modulating the signal at an equipment input port results in
more than 2 errored seconds in a 30-second measurement interval. Requirements on
input jitter tolerances are then given in terms of a jitter tolerance mask, which represents
the minimum acceptable jitter tolerances for a specified range of jitter frequencies.
There are two different jitter tolerance masks defined for Category I (SONET interfaces)
and Category II (non-SONET interfaces) equipment.
GR-253-CORE Jitter Tolerance Requirements (STS-1)
For Category I interfaces, the same requirements are used as defined in GR-499-CORE.
For Category II interfaces that are specified as having reduced jitter tolerance, shall
tolerate, as a minimum, input jitter applied according to the mask given in Table 10.
4.1.8
Receive Output Jitter
The intrinsic jitter of the receiver output signal RDOP/RDON/RCLK (if no input jitter is
applied) is
•
•
•
E3:
< 0.06 UI
DS3:
< 0.08 UI
STS-1: < 0.10 UI
Data Sheet
37
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.2
Transmitter
The serial bit stream is then processed by the transmitter which has the following
functions:
•
•
generation of AMI, B3ZS (DS3/STS-1) or HDB3 (E3) coded signals
all-ones generation (alarm indication signal)
4.2.1
Transmit Line Interface
The received data stream on pins XDIP (single rail data) or XDIP/XDIN (dual rail data) is
converted into a ternary signal which is output on pins XL1 and XL2. In E3 mode the
HDB3 and AMI line code are supported, in DS3/STS-1 mode the B3ZS and AMI is
supported.
R1
t1 : t2
75 Ω
XL1
TE3-LIUTM
CP
R1
XL2
F0079
Figure 13
Transmitter Configuration
Table 11
External Component Values for Transmitter
Parameter
Characteristic Line Impedance [Ω]
DS3
STS-1
E3
75
R1 (± 1 %) [Ω]
37.51)
Cp [pF]
372)
t2 : t1
1:1
1) This value refers to an ideal transformer without any parasitics. Any transformer resistance or other parasitic
resistances have to be taken into account when calculating the final value for the output serial resistors.
2) This value includes all parasitic capacitances on the secondary side of the transformer.
The external components are the same for DS3, STS-1 and E3 applications. Transmit
return loss requirements for E3 defined in ETS 300 166 are fulfilled. Pulse mask
Data Sheet
38
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
requirements according to ANSI T1.102 (at cross connect point, up to 450 ft.) are
fulfilled.
Note: An additional capacitor on the primary or secondary side of the transformer may
be required in some applications to improve the pulse mask, if the parasitic
capacitances of the PCB are very small.
Table 12
E3 Transmit Return Loss
Return Loss1)
Frequency Range
from [kHz]
to [kHz]
[dB]
860
1720
6
1720
51550
8
1) measured with an unframed PRBS 215-1 pattern
4.2.2
Transmit Clock System
The supplied transmit clock XCLK is duty-cycle corrected by an internal PLL circuit to
provide a 50% clock signal to the internal line driver unit. The pulse shaper working
frequency is fourfold of the XCLK frequency.
If the transmit clock XCLK is failing, an all-zero signal is generated automatically.
If AIS insertion is selected, the output signal is referenced to REFCLK.
XAIS
fnom
REFCLK
XTAL1
XTAL2
XCLK
XDIP
XDIN
Transmit
PLL
fnom : 3
JATT
Jitter
Attenuator
PLL
disable
testmode
XAIS
Encoder
AIS
Insertion
fnom
fnom x 4
fnom
Jitter
Attenuator
Buffer
Pulse
Shaper
Line Driver
XL1
XL2
F0232
Figure 14
Data Sheet
Transmit Clock System
39
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.2.3
Jitter Attenuation
Jitter is reduced in transmit direction, if the jitter attenuator is activated (JATT = 1). The
JATT control signal enables/disables the jitter attenuation PLL and activates/bypasses
the buffer.
The jitter attenuator consists of a buffer and a PLL. The jitter attenuation PLL delivers a
"jitter free" clock (nominal frequency divided by 3, see Table 13) to the transmit PLL
which generates the buffer read clock. The jitter attenuation PLL uses a pullable crystal
and supports a tuning range of ± 150 ppm.
The jitter attenuator uses a 64-bit dual rail buffer and fulfills the requirements of GR-499CORE and GR-253-CORE as shown in Figure 15. This covers the requirements of ITUT G.751, G.752 and G.755 as well.
To avoid the need for a high frequency crystal, the reference clock for the jitter
attenuation PLL is only one third of the nominal frequency. A detailed block diagram of
the transmit clocking is given in Figure 14.
Table 13
Jitter Attenuation PLL Operation Frequencies
Operation mode
Jitter Attenuation
PLL Input
Frequency
Jitter Attenuation
PLL Output
Frequency
Crystal Frequency
DS3
44.736 MHz
14.912 MHz
14.912 MHz
STS-1
51.840 MHz
17.280 MHz
17.280 MHz
E3
34.368 MHz
11.456 MHz
11.456 MHz
Further requirements for the external crystal are found in Table 21 on page 54.
Data Sheet
40
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
20 dB/decade
Jitter Gain
0.5 dB
0.1 dB
ITU-T G.755 &
GR-499-CORE
ITU-T G.751
- 20 dB
TE3-LIU
ITU-T G.752
- 40 dB
GR-253-CORE
10
40
100 300
1000
Jitter Frequency
Figure 15
4.2.4
10000
100000
15000
F0141
Jitter Attenuation Characteristic
Intrinsic Jitter
The TE3-LIU™ transmit PLL generates an output jitter which fulfills the requirements as
specified in Table 14 below.
Table 14
Transmit Output Jitter
Specification
Measurement Filter Bandwidth
Output Jitter1)
Lower Cutoff
Upper Cutoff
GR-499-CORE
(DS3)
10 Hz
300 kHz
ANSI T1.404
(DS3)
10 Hz
400 kHz
< 0.5 UIPP
30 kHz
400 kHz
< 0.05 UIPP
GR-253-CORE
(STS-1)
12 kHz
400 kHz
< 1.0 UIPP
ETSI TBR24
(E3)
100 Hz
800 kHz
< 0.4 UIPP
10 kHz
800 kHz
< 0.15 UIPP
< 1.0 UIPP
< 0.3 UIrms
< 0.3 UIrms
1) Measured with maximum input jitter applied (see Figure 12).
Data Sheet
41
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.2.5
Pulse Shaper
The internal pulse shaper generates the required pulse shapes for E3, DS3 and STS-1
signals according to ANSI T1.102, T1.404, Telcordia GR-499-CORE and ITU-T G.703).
The specific pulse mask is fulfilled at the crossconnect point at a distance of 0 to 450 ft.
to the transmitter (DS3 requirement).
The maximum line length between a TE3-LIU™ transmitter and TE3-LIU™ receiver is
1100 ft. for a coaxial cable of AT&T type 728A, 734A or 734D.
4.2.6
Transmit Line Coding
4.2.6.1
AMI Code
The AMI code is defined as a dual rail data signal, where the combinations 00 ("0"), 10
("+1") and 01 ("-1") are valid. Additionally no subsequent "+1" or "-1" bits are allowed
(bipolar violations). A dual rail data stream is passed transparently, even if it contains
bipolar violations. A single rail data stream is encoded to a correct AMI coded bipolar
data stream without zero code suppression.
4.2.6.2
B3ZS Code
In the B3ZS line code each block of three consecutive zeros is replaced by either of two
replacements codes which are B0V and 00V, where B represents a pulse which applies
to the bipolar rule ("+1" or "-1") and V represents a bipolar violation (two consecutive "+1"
or "-1" bits). The replacement code is chosen in a way that there is an odd number of
valid B pulses between consecutive V pulses to avoid the introduction of a DC
component into the analog signal.
The transmit line encoder detects three-zeros pattern sequences and changes them to
the appropriate replacement pattern.
Although B3ZS coding is normally used with single rail NRZ data, the transmit line
encoder accepts either dual rail or single rail data. Bipolar violations in an incoming dual
rail data stream are converted to valid data pulses.
4.2.6.3
HDB3 Code
In the HDB3 line code each block of four consecutive zeros is replaced by either of two
replacements codes which are B00V and 000V, where B represents a pulse which
applies to the bipolar rule ("+1" or "-1") and V represents a bipolar violation (two
consecutive "+1" or "-1" bits). The replacement code is chosen in a way that there is an
odd number of valid B pulses between consecutive V pulses to avoid the introduction of
a DC component into the analog signal.
The transmit line encoder detects three-zeros pattern sequences and changes them to
the appropriate replacement pattern.
Data Sheet
42
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
Although HDB3 coding is normally used with single rail NRZ data, the transmit line
encoder accepts either dual rail or single rail data. Bipolar violations in an incoming dual
rail data stream are converted to valid data pulses.
4.2.7
AIS Insertion
An unframed all-ones signal can be inserted into the transmitted data stream. To fulfill
the required accuracy, a reference clock of ± 20 ppm is needed on pin REFCLK.
If local loop configuration and AIS insertion is selected together, the AIS signal is looped
back to RDOP/RDON.
4.3
Framer Interface
The interface to the receive framer is realized by RDOP, RDON and RCLK. Data at
RDOP/N are clocked off with either the rising (RPE=1) or falling edge (RPE=0) of RCLK.
Alternatively a single rail signal can be selected to be output on pin RDOP (DR/SR=0).
Bipolar violation indications are output on pin RDON/BPV in this case.
Data from the framer interface are sampled at XDIP and XDIN on the active edge of the
XCLK. The active edge can be the rising (XPE=1) or falling edge (XPE=0) of XCLK.
Alternatively a single rail signal can be used on pin XDIP (DR/SR=0).
Note: Selection of dual rail/single rail mode is common to receive and transmit direction.
See Figure 24 on page 56 and Figure 25 on page 57 for details.
Data Sheet
43
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.4
Maintenance Functions
4.4.1
Remote Loop
In the remote loopback mode the clock and data recovered from the line inputs RL1/2
are routed back to the line outputs XL1/2. As in normal mode they are also processed by
the synchronizer and then sent to the framer interface. Data passes the decoder and
encoder circuit. The recovered receive clock is used to drive the transmit pulse shaper.
RL1
RL2
Noise &
Crosstalk
Filter
Equalizer
Clock &
Data
Recovery
RDON
RDOP
RCLK
Decoder
Remote
Loop
XL1
XL2
Line
Driver
Pulse
Shaper
Jitter
Attenuator
Encoder
XDIN
XDIP
XCLK
F0083
Figure 16
Remote Loop Signal Flow
Notes
1. If remote loop and local loop are selected simultaneously, the device will be set into
power down mode.
2. The jitter attenuator can be switched off optionally.
Data Sheet
44
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Interface Description
4.4.2
Local Loop
The local loopback mode disconnects the receive lines RL1/2 from the receiver. Instead
of the signals coming from the line data provided by system interface is routed through
the analog receiver back to the framer interface. The transmit bit stream is sent to the
transmit line unchanged. If XAIS=1 is selected, the transmit data stream is replaced by
an all-ones signal and looped back.
RL1
RL2
Noise &
Crosstalk
Filter
Equalizer
Clock &
Data
Recovery
Decoder
RDON
RDOP
RCLK
Line
Driver
Pulse
Shaper
Jitter
Attenuator
Encoder
XDIN
XDIP
XCLK
Local
Loop
XL1
XL2
F0084
Figure 17
Local Loop Signal Flow
Notes
1. If remote loop and local loop are selected simultaneously, the device will be set into
power down mode.
2. The jitter attenuator can be switched off optionally.
Data Sheet
45
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Operational Description
5
Operational Description
5.1
Operational Overview
The TE3-LIU™ can be operated in three principle modes, which are either E3, DS3 or
STS-1 mode. This basic operation mode selection has to be stable before the reset
signal goes inactive.
The device is programmable by pin selection. Direct connection to a microprocessor
data bus is possible by using the chip select pin (CS) as a write strobe.
5.2
Device Reset
The TE3-LIU™ is forced to the reset state if a low signal is input on pin RES (for minimum
period see page Page 51). During reset, all output stages are in a high impedance state,
all internal flip-flops are reset.
The basic device mode (DS3, STS-1 or E3, jitter attenuation) has to be selected during
reset to enable the internal PLLs to adjust.
After reset all control input values are cleared. The default control values (driven by
internal pullups) are activated after CS = low is applied for the first time after reset.
5.3
Device Power Down
The TE3-LIU™ can be set into power down state to reduce power consumption, if not
active. Power down mode is selected by setting RL=LL=1. Receive and transmit circuits
are switched off including internal PLLs and transmit line driver. Recovery from power
down mode is achieved by clearing either of RL or LL (RL = 0 and/or LL = 0). After
recovery from power down, the internal PLLs need to stabilize again. REFCLK must be
active to recover from power down mode.
Internal pullup resistors are not switched off during power down to prevent open input
lines from floating.
Note: If switching directly from local loop to remote loop or vice versa, make sure that
there is no signal overlap, which would set the device into power down mode
unintentionally.
5.4
Transmit Line Inactive
If the transmitter is not used, it can be switched into inactive mode by setting XLT=1.
During inactive state the common mode voltage of 1.5 V is output on XL1 and XL2. The
transmit PLL is not stopped and output can be enabled again by XLT=0 without wait time.
Data Sheet
46
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6
Electrical Characteristics
6.1
Absolute Maximum Ratings
Table 15
Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Ambient temperature under bias
TA
Tstg
VDD
VDDR
VDDX
VSO
– 40 to 85
°C
– 65 to 150
°C
– 0.4 to 4.5
V
– 0.4 to 4.5
V
– 0.4 to 4.5
V
– 0.4 to 4.5
V
Voltage on any input pin with
respect to ground
VSI
– 0.4 to 5.5
V
ESD robustness1)
HBM: 1.5 kΩ, 100 pF
VESD,HBM
2000
V
Storage temperature
IC supply voltage (digital)
IC supply voltage receive (analog)
IC supply voltage transmit (analog)
Voltage on any output pin
with respect to ground
1) According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.
Attention: Stresses above those listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Data Sheet
47
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.2
Table 16
Operating Range
Power Supply Range
Parameter
Ambient temperature
Supply voltage
Digital input voltages
Ground
Symbol Limit Values
TA
VDD
VDDR
VDDX
VDDRP
VDDXP
VID
VSS
VSSR
VSSX
VSSRP
VSSXP
Unit Condition
Min.
Max.
-40
85
°C
3.13
3.46
V
3.3 V ± 5%
0
5.25
V
5.0 V + 5%
0
0
V
Notes
1. In the operating range, the functions given in the circuit description are fulfilled.
All VDD pins have to be connected to the same voltage level,
All VSS pins have to be connected to ground level.
2. Typical characteristics specify mean values expected over the production spread. If
not otherwise specified, typical characteristics apply at TA = 25 °C and 3.3V supply
voltage.
Data Sheet
48
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.3
Table 17
DC Characteristics
DC Parameters
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Average power
supply current
Symbol Limit Values
VIL
VIH
VOL
VOH
IDD
Unit Notes
Min.
Max.
– 0.4
0.8
V
2.0
5.25
V
0.45
V
2.4
V
110 (typ.)
mA
155 (typ.)
Input leakage current
Input leakage current
Input pullup current
IIL11
IIL12
IIPU
2
IOL = + 4 mA1)
IOH = – 4 mA 1)
typical (DS3,
PRBS, JATT
enabled, 3.3 V)
worst case (STS-1,
JATT enabled, AIS,
3.46 V)
1
µA
1
µA
25
µA
VIN = VDD2)
VIN = VSS2)
VIN = VSS
µA
VIN = VDD
1
mA
XL1/2 = VDDX,
XLT = 1
1
mA
XL1/2 = VSSX,
XLT = 1
200
µA
XL1/2 = 1.50 V3),
XLT = 1
applies to XL1and
XL24)
5 (typ.)
Input pulldown current
IIPU
–2
– 25
-5 (typ.)
Transmitter leakage
current
ITL
RX
5 (typ.)
Ω
Differential peak voltage of VX
a mark (at XL1/XL2)
2.0
V
Transmitter output
impedance
Receiver differential peak
voltage of a mark
(at RL1/RL2)
VR
VDDR+0.3 V
Receiver input impedance ZR
Data Sheet
1 (typ.)
49
kΩ
RL1, RL2
3)4)
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
Table 17
DC Parameters (cont’d)
Parameter (cont’d)
Receiver sensitivity
Analog loss of Signal
threshold E3
Symbol Limit Values
SRSH
VLOS3
Unit Notes
Min.
Max.
0
13
-35
dB
– 15
RL1, RL2
dB
1) applies to all output pins except analog pins XL1/XL2
2) Input leakage currents of pins containing internal pullup devices are measured in a testmode which switches
off the pullups.
3) test against common mode voltage, parameter not tested in production
4) parameter not tested in production
Data Sheet
50
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.4
AC Characteristics
6.4.1
Reset
1
RES
2
DS3/E3
DS3/STS-1
JATT
3
(PLLs tuned)
F0095
Figure 18
Reset Timing
Table 18
Reset Timing Parameter Values
No.
Parameter
Limit Values
Min.
Unit
Max.
1
RES pulse width low
10
µs
2
DS3/E3, DS3/STS-1, JATT to RES setup
time
5
ns
3
PLL startup time
1000
µs
Note: REFCLK must be active during reset.
Data Sheet
51
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.4.2
Reference Clock
1
2
3
REFCLK
4
5
F0107
Figure 19
Reference Clock Timing
Table 19
REFCLK Timing Parameter Values
No.
Parameter
Limit Values
Min.
1
Typ.
Unit
Max.
REFCLK period E3
29.1
ns
REFCLK period DS3
22.4
ns
REFCLK period STS-1
19.3
ns
2
REFCLK high
20
80
%
3
REFCLK low
20
80
%
4
REFCLK rise time
41)
ns
1)
ns
5
REFCLK fall time
4
Clock accuracy
20
2)
ppm
1) not tested in production
2) if DS3-AIS function is not required, 200 ppm is sufficient to guarantee correct receive PLL function
Data Sheet
52
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.4.3
Jitter Attenuator Reference Clock
1
2
3
XTAL1
4
5
F0164
Figure 20
XTAL Clock Timing
•
Table 20
No.
XTAL Timing Parameter Values
Parameter
Limit Values
Min.
1
Typ.
Unit
Max.
XTAL1/2 period E3
87.29
ns
XTAL1/2 period DS3
67.06
ns
XTAL1/2 period STS-1
57.87
ns
CL
XTAL1
TE3-LIUTM
CL
XTAL2
DS3: 14.912 MHz
STS-1: 17.280 MHz
11.456 MHz
E3:
F0245
Figure 21
Data Sheet
Recommended Crystal Circuit
53
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
+200
f - f0
f0
+100
[ppm]
0
pulling range
+150
nominal value
+50
-50
-100
-150
-200
10
15
20
Load Capacitance CLeff [pF]
F0259
Figure 22
Crystal Pulling Range
Table 21
XTAL Crystal Parameter Values
No.
Parameter
Limit Values
Min.
1
Typ.
Unit
Max.
Crystal nominal frequency DS3
14.912
MHz
Crystal nominal frequency STS-1
17.280
MHz
Crystal nominal frequency E3
11.456
MHz
2
Crystal motional capacitance C1
25
fF
3
Crystal shunt capacitance C0
7
pF
15
pF
1)
4
Crystal load capacitance CLeff
5
Crystal resonance resistance Rr
6
Internal parasitic load capacitance CLint
30
7.5
Ω
pF
1) This value includes the capacitance of the external capacitors (CLext) plus all internal (CLint) and external
parasitic capacitances (CLpara). The value of the external capacitor has to be chosen depending on the printed
circuit board layout. A typical value for CL is 0 to 10 pF, CL should be adapted to the parasitics to achieve a
symmetrical pulling range.
Note: CLeff = CLext + CLint + CLpara
CLext = 0.5 x CL
Data Sheet
54
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.4.4
Microprocessor Control
1
2
CS
3
4
Control Signal
F0097
Figure 23
Chip Select Timing
Table 22
Chip Select Timing Parameter Values
No.
Parameter
Limit Values
Min.
1
2
Unit
Max.
2.5 × TRCLK
CS pulse width low
E1 73
ns
DS3 56
ns
STS-1 50
ns
2.5 × TRCLK
CS pulse width high
E1 73
ns
DS3 56
ns
STS-1 50
ns
3
Control Signal Setup Time
10
ns
4
Control Signal Hold Time
10
ns
Data Sheet
55
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.4.5
Transmit Input Timing
1
2
3
XCLK (XPE=0)
6
7
XCLK (XPE=1)
data change edge
4
5
XDIP, XDIN
F0090
Figure 24
XCLK Input Timing
Table 23
XCLK Timing Parameter Values
No.
Parameter
Limit Values
Min.
1
Typ.
Unit
Max.
XCLK period E3
29.1
ns
XCLK period DS3
22.4
ns
XCLK period STS-1
19.3
ns
2
XCLK high
30
70
%
3
XCLK low
30
70
%
4
XDIP, XDIN setup time
2
ns
5
XDIP, XDIN hold time
2
ns
6
XDIP, XDIN, XCLK rise time
11)
ns
7
XDIP, XDIN, XCLK fall time
11)
ns
8
Clock accuracy
202)
ppm
1) not tested in production
2) if DS3-AIS function is not required, 200 ppm is sufficient to guarantee correct PLL function
Data Sheet
56
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.4.6
Receive Output Timing
1
2
3
RCLK (RPE=0)
5
6
RCLK (RPE=1)
4
RDOP, RDON
data change edge
F0108
Figure 25
RCLK Output Timing
Table 24
RCLK Timing Parameter Values
No.
Parameter
Limit Values
Min.
1
Typ.
Unit
Max.
RCLK period E3
29.11)
ns
RCLK period DS3
22.41)
ns
RCLK period STS-1
19.31)
ns
2
RCLK high
40
50
60
%
3
RCLK low
40
50
60
%
2
2)
ns
5
2)
ns
5
2)
ns
4
5
6
RDOP, RDON delay time
0
RDOP, RDON, RCLK rise time
1
2
RDOP, RDON, RCLK fall time
2
1) applies only while the receiver PLL is locked to a valid signal on RL1/RL2, e.g., not in case of LOS
2) not tested in production
Data Sheet
57
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.4.7
Pulse Templates
6.4.7.1
Pulse Template E3
17 ns
(14.55 + 2.45)
1.0
0.2
8.65 ns
(14.55 – 5.90)
0.2
0.1 0.1
V
Nominal pulse
14.55 ns
0.5
12.1 ns
(14.55 – 2.45)
0.1
0.1
0.2
0.1
0
0.1
24.5 ns
(14.55 + 9.95)
29.1 ns
T1818860-92
(14.55 + 14.55)
FIGURE 17/G.703
Pulse mask at the 34 368-kbit/s interface
Figure 26
E3 Pulse Shape at Transmitter Output
Table 25
E3 Pulse Mask1)
No.
F0076
Parameter
Limit Values
Min.
Nominal peak voltage of a mark (pulse)
Typ.
Max.
1.0
Peak voltage of a space (no pulse)
V
- 0.1
Nominal pulse width
0.1
14.55
Amplitude ratio of positive to negative pulses2)
3)
Pulse width ratio of positive to negative pulses
Unit
V
ns
0.95
1.05
0.95
1.05
1) measured at the output port without transmission line and 75Ω load;
bit sequence: 0000000(+1)0000000(-1)0000000(+1)0000000(-1)...
2) at the center of a pulse interval
3) at the nominal half amplitude
Data Sheet
58
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.4.7.2
Pulse Template DS3
1.2
1.0
Normalized Amplitude
0.8
0.6
GR-499-CORE
0.4
0.2
ANSI T1.404
0
-0.2
-1.0
-0.5
0
0.5
1.0
1.5
Time [unit intervals]
F0077
Figure 27
DS3 Pulse Shape at the Cross Connect Point (450 ft.)
Table 26
DS3 Pulse Mask (ANSI T1.404, GR-499-CORE)1)
Absolute Voltage Level (100 % Value)
Min.
Max.
0.36 V
0.85 V
1) bit sequence: 0000000(+1)0000000(-1)0000000(+1)0000000(-1)...
Data Sheet
59
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
Table 27
DS3 Pulse Mask (ANSI T1.404)
Lower Curve
Time
Equation
T ≤ -0.36
-0.03
-0.36 ≤ T ≤ +0.36
π
T
0.5 1 + sin --- 1 + ----------- – 0.03
2
0.18
T ≥ +0.36
-0.03
Upper Curve
Time
Equation
T ≤ -0.68
+0.03
-0.68 ≤ T ≤ +0.36
π
T
0.5 1 + sin --- 1 + ----------- + 0.03
2
0.34
T ≥ +0.36
Table 28
0.05 + 0.407 × e -1.84 [ T – 0.36 ]
DS3 Pulse Mask (GR-499-CORE)
Lower Curve
Time
Equation
-0.85 ≤ T ≤ -0.36
-0.03
-0.36 ≤ T ≤ +0.36
π
T
0.5 1 + sin --- 1 + ----------- – 0.03
2
0.18
+0.36 ≤ T ≤ +1.4
-0.03
Upper Curve
Time
Equation
-0.85 ≤ T ≤ -0.68
+0.03
-0.68 ≤ T ≤ +0.36
π
T
0.5 1 + sin --- 1 + ----------- + 0.03
2
0.34
+0.36 ≤ T ≤ +1.4
Data Sheet
0.08 + 0.407 × e -1.84 [ T – 0.36 ]
60
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.4.7.3
Pulse Template STS-1
1.2
1.0
Normalized Amplitude
0.8
0.6
0.4
0.2
0
-0.2
-1.0
-0.5
0
0.5
1.0
1.5
Time [unit intervals]
F0109
Figure 28
STS-1 Pulse Shape at the Cross Connect Point (450 ft.)
Table 29
STS-1 Pulse Mask1)
Signal Power
Min.
Max.
- 2.7 dBm
+ 4.7 dBm
1) bit sequence: (+1)0(-1)0(+1)0(-1)...
Table 30
STS-1 Pulse Mask (ANSI T1.102)
Lower Curve
Data Sheet
Time
Equation
-0.85 ≤ T ≤ -0.38
-0.03
-0.38 ≤ T ≤ +0.36
π
T
0.5 1 + sin --- 1 + ----------- – 0.03
2
0.18
+0.36 ≤ T ≤ +1.4
-0.03
61
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
Upper Curve
Time
Equation
-0.85 ≤ T ≤ -0.68
+0.03
-0.68 ≤ T ≤ +0.26
π
T
0.5 1 + sin --- 1 + ----------- + 0.03
2
0.34
+0.26 ≤ T ≤ +1.4
Data Sheet
0.1 + 0.61 × e -2.4 [ T – 0.26 ]
62
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.5
Table 31
Capacitances
Pin Capacitances
Parameter
Symbol
Limit Values
Min.
Max.
Unit Notes
CIN
5
10
pF
1)
COUT
8
15
pF
all except XL1, XL2
1)
COUT
8
20
pF
XL1, XL2
1)
Input capacitance
Output capacitance
Output capacitance
1) not tested in production
6.6
Package Characteristics
F0051
Figure 29
Thermal Behavior of Package
Table 32
Package Characteristic Values
Parameter
Symbol
Limit Values
Min.
Typ.
Thermal Resistance1)
Junction to Ambient
RthJA
63
Thermal Resistance2)
Junction to Case
RthJC
15
Junction Temperature
Rj
Unit Notes
Max.
K/W single layer PCB,
30%/11 µm
K/W metallization,
1W, no convection
125
°C
1) RthJA = (Tjunction - Tambient)/Power
not tested in production
2) RthJC = (Tjunction - Tcase)/Power
not tested in production
Data Sheet
63
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Electrical Characteristics
6.7
Test Configuration
AC Test Level
External Load
Device
under
Test
VT
Drive Levels
CL
Timing Test
Points
VIH
F0206
VIL
Figure 30
Input/Output Waveforms for AC Testing
Table 33
AC Test Conditions
Parameter
Symbol Test
Values
Unit Notes
Load Capacitance 1
CL1
50
pF
digital outputs except
RDOP, RDON, RCLK
Load Capacitance 2
CL2
15
pF
digital outputs RDOP,
RDON and RCLK
Load Capacitance 3
CL3
50
pF
analog line output
XL1, XL2
Input Voltage high
VIH
2.4
V
all except RL1, RL2
Input Voltage low
VIL
0.4
V
all except RL1, RL2
Test Voltage
VT
VDD/2
V
all except XL1, XL2
Output Test Load
RL
75 ± 5%
Ω
XL1, XL2
Rise Times
TR
10 - 90
%
Fall Times
TF
90 - 10
%
not tested in
production
Notes
1. Typical characteristics are mean values expected over the production spread. If not
specified otherwise, typical characteristics apply at TA = 25 °C and VDD = 3.3V.
2. Capacitance values include all parasitics caused by board layout, transformer etc.
Data Sheet
64
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Package Outlines
7
Package Outlines
GPM05622
P-MQFP-44-2
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
65
Dimensions in mm
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Appendix
8
Appendix
8.1
Cable Characteristics
Cable characteristics are defined in ANSI T1.102 as shown below.
Office Cable Loss (450 ft. coaxial)
14
12
Insertion Loss [dB]
10
8
6
4
2
0
1
10
100
Frequency [MHz]
Office Cable Insertion Phase (450 ft. coaxial)
90
80
Insertion Phase [deg]
70
60
50
40
30
20
10
0
1
10
100
Frequency [MHz]
F0105 V1.1
Figure 31
Data Sheet
DS3 Cable Characteristics
66
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Appendix
8.2
Application Example
The following picture shows a typical application circuit (excluding surge protection).
Jitter
Attenuation
Reference
CL
CL
XTAL1/2
VDDRP/VSSRP
VDDR/VSSR
DS3/STS-1/E3
Receive Line
Interface
RL1/2
Receive Path
RDOP
RDON
RCLK
LOS
DS3/STS-1/E3
Framer/Mapper
Receive
Interface
XDIP
XDIN
XCLK
DS3/STS-1/E3
Framer/Mapper
Transmit
Interface
TE3-LIUTM V1.3
DS3/STS-1/E3
Transmit Line
Interface
Transmit Path
XL1/2
VDDXP/VSSXP
VDDX/VSSX
VDD/VSS
REFCLK
Reference
Clock
Figure 32
Data Sheet
TEST
N.C. Control Interface
F0233
Application Circuit
67
Rev. 2, 2005-01-24
PEF 3452
TE3-LIU V1.3
Index
Loss of Signal
A
M
AIS 20
Ambient temperature
AMI 35
ANSI 9, 72
Applications 12, 14
MIL-Std 883D
53
Operating Range
Output Jitter 40
53
P
Package 68, 71
PLL 57
P-MQFP-44-2 71
Power Down 52
Power Supply 23, 53
Pulse Shaper 47
Pulse Template DS3 65
Pulse Template E3 64
Pulse Template STS-1 67
35
44
C
Cable 72
Clock 17, 19
Clock and Data Recovery
crystal 44, 59
34
E
Edge Selection 21
ESD 53
External Component Values
R
RCLK 63
Receive Clock 17
Receive Data 17
Receive Line Interface 17, 33
Receive Return Loss 33
Receiver 31
Reference Clock 19, 58
Remote Loop 21, 50
Reset 20, 52, 56, 61
31, 32
H
HDB3
53
O
B
B3ZS
buffer
22
35
I
Input Jitter 38
international standards
intrinsic jitter 34
ITU-T 9
9
S
Supply voltage
J
T
JATT 44
Jitter Attenuation 19, 22, 44, 45
Jitter Tolerance 38, 39
TAP Controller 24
Temperature 12
Thermal Behaviour 68
Transmit Clock 18
Transmit Data 18
Transmit Line 52
Transmit Line Interface 18, 41
L
Line Coding 20, 35
Line Monitoring 21, 32
Local Loop 21, 51
Data Sheet
53
68
2005-01-24
PEF 3452
TE3-LIU V1.3
W
wander
38
X
XCLK 62
XTAL 59
Data Sheet
69
2005-01-24
w w w . i n f i n e o n . c o m
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